Clera
Senior Silicon Engineer
- Compensation
- $200K–$300K / yr
- From job posting
- Location
- San Francisco, CA, US
- Arrangement
- On-site
- Employment type
- Full-time
- Level
- Senior
- Posted
- 15 October 2026 (today)
Checked todayApplications go to the employer, never to RoleSprint
About this role
ABOUT THE ROLE
Lead silicon design for an AI accelerator, taking designs from FPGA prototypes through ASIC tapeout and bring-up. As a senior member of a small hardware team, you will shape technical direction across architecture, RTL, verification, and tooling, working closely with PCB, interconnect, software, and systems teams.
WHAT YOU'LL DO
- Lead FPGA prototype development and optimization, from design specifications through deployment on working hardware.
- Design and review synthesizable RTL for an ASIC, with a focus on clean microarchitecture.
- Build and improve lint, simulation, synthesis, timing, and verification flows for rapid iteration and tapeout readiness.
- Make architecture decisions across compute datapaths, memory systems, on-chip interconnect, and control logic.
- Drive design through tapeout, bring-up, and delivery milestones, contributing hands-on during critical periods.
- Mentor teammates and help grow the silicon engineering team.
WHAT WE'RE LOOKING FOR
- At least 8 years of experience in digital design or silicon engineering, building RTL, FPGA prototypes, or ASICs.
- Experience shipping synthesizable SystemVerilog or Verilog in production silicon or FPGA designs, and taking FPGA designs from RTL through synthesis, place-and-route, and deployment to working hardware.
- Strong understanding of digital design, including pipelining, clocks, resets, latency, throughput, and microarchitecture.
- Experience designing compute datapaths and memory systems with bandwidth and latency constraints.
- Hands-on experience with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification.
- Experience automating hardware flows with Python, Tcl, Make, Nix, or similar tools, plus background in AI accelerators or low-level AI kernels.
- Tapeout experience, high-speed interfaces, formal verification, UVM, cocotb, firmware, or systems-level hardware drivers are valuable.
COMPENSATION & BENEFITS
Base salary is $200,000 to $300,000 USD annually. Visa sponsorship is available.
LOCATION
Full-time, on-site role in San Francisco, United States. This position is not remote or hybrid.
Work location
- San Francisco, CA, US
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About this listing
Published on Ashby under the board identifier Clera, which is the name the employer’s own job board carries. RoleSprint has not verified the company’s registered or trading name, so it is shown exactly as published rather than tidied up.
RoleSprint is not the employer and not a recruiter. Applications are made on the employer’s own site and never reach us; what RoleSprint does is help you decide whether a role is worth your time and prepare for it if it is.
Published 15 October 2026, last checked today. A posting stops being advertised here 90 days after the employer published it, and one the employer takes down is marked closed rather than quietly removed.