Clera
Senior Silicon Engineer
- Compensation
- $200K–$300K / yr
- From job posting
- Location
- San Francisco, CA, US
- Arrangement
- On-site
- Employment type
- Full-time
- Level
- Senior
- Posted
- 1 October 2026 (today)
Checked todayApplications go to the employer, never to RoleSprint
About this role
ABOUT THE ROLE
As a founding silicon team member at a well-funded AI accelerator startup, you will lead the full journey of a custom XPU from FPGA prototype through tapeout and bring-up. This is a high-ownership, high-impact role that sets technical direction across architecture, RTL, verification, and tooling while the silicon organization grows around you.
WHAT YOU'LL DO
- Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon.
- Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code.
- Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness.
- Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic.
- Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods.
- Grow and mentor the silicon team as the company scales.
WHAT WE'RE LOOKING FOR
- 8 or more years of hands-on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs.
- Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs.
- End-to-end FPGA experience: RTL through synthesis, place-and-route, and deployment to working hardware.
- Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture.
- Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows.
- Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools.
- Background designing or optimizing AI accelerators or low-level AI kernel implementations.
- Tapeout experience, high-speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages.
- Self-directed, comfortable with ownership, and energized by fast-moving environments.
COMPENSATION & BENEFITS
Base salary range: $200,000 to $300,000 USD annually, plus equity. Visa sponsorship is available.
LOCATION
Full-time, on-site in San Francisco, CA. This role is not remote or hybrid.
Work location
- San Francisco, CA, US
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About this listing
Published on Ashby under the board identifier Clera, which is the name the employer’s own job board carries. RoleSprint has not verified the company’s registered or trading name, so it is shown exactly as published rather than tidied up.
RoleSprint is not the employer and not a recruiter. Applications are made on the employer’s own site and never reach us; what RoleSprint does is help you decide whether a role is worth your time and prepare for it if it is.
Published 1 October 2026, last checked today. A posting stops being advertised here 90 days after the employer published it, and one the employer takes down is marked closed rather than quietly removed.